指令cache分析,I-cache
1)I-cache指令cache分析
1.8e,chooses the extra reduction steps(ERs)in Montgomery Modular Multiplication Algorithm during the entire execution of RSA as the breakthrough entry,bases on the theoretical foundation that the ERs will be changed as the difference of the secret key bits,prefers to useI-cache analysis as our tool to detect the occurrences of ERs,and finally recovers the original key.8e实现的RSA密码系统解密/签名执行过程为攻击对象,以RSA密码实现过程中利用的蒙哥马利模乘算法中的额外约简步骤为突破点,以随着密钥位的不同而会产生不同的约简步骤为理论基础,将指令Cache分析作为检测额外约简步骤发生的工具进行密码分析,最终恢复原始密钥,从而证明指令cache分析,对成功实施RSA密码攻击的可行性。
2)instruction cache指令Cache
1.To improve the operating efficiency of general micro processors,the architecture and design method ofinstruction cache are investigated.为提高通用微处理器的执行效率,研究了高性能指令Cache的体系结构和设计方法。
2.Most modern microprocessors employ on-chip caches to bridge the enormous speed disparities between the main memory and central processing unit (CPU), but these caches consume a significant fraction of total energy dissipation, especially the power dissipated byinstruction cache itself is often a significant part of the power dissipated by the entire on-chip caches.现代微处理器大多采用片上Cache来缓解主存储器与中央处理器(CPU)之间速度的巨大差异,但Cache也成为处理器功耗的主要来源,尤其是其中大部分功耗来自于指令Cache。
3.Instruction prefetching is an effective mechanism to reduce theinstruction cache miss rate.指令预取技术能够有效地降低指令Cache的访问失效率,提高微处理器的取指令能力,进而提高微处理器的性能。
英文短句/例句
1.Designed technology of instruction cache based on pipeline;基于流水线的指令Cache设计技术
2.An I-cache Attack Method on RSA Implementation针对RSA密码算法的指令Cache攻击方法
3.Study and Implement on Code Reordering Technology of I-Cache Optimization;指令Cache优化中代码重排技术的研究与实现
4.Synchronization technology based on invalidation of instruction Cache for multi-core processor基于指令Cache作废的多核处理器同步技术
5.Design and System-level Verification of Instruction CACHE Architure;指令CACHE结构设计与系统级验证
6.Vector Instruction Set Optimized for Cache面向Cache优化的向量指令集设计与测评
7.To issue orders or commands.命令颁布命令或指令
bination order/combo order组合指令,选择性指令
9.An instruction sequence in programmed instruction.指令程序编排指令中的指令次序
10.The act or an instance of enjoining;a command, a directive, or an order.命令，指令命令的动作或例子；命令，指令或训谕
11.assembler directive汇编命令,汇编指令
12.orders per second每秒的指令数;每秒指令数;每秒钟的指令数目
13.External Command Output【计】外部指令输出
14.KNI Katmai New InstructionsKatmai新指令集，即SSE
15.instruction repertoire(计算机)指令系统
16.tional stop instruction条件停机指令;任选停止指令;选择停机指令;随意停机指令
17.An authoritative command or order.命令有权威的训令或指令
18.shippers" order托运人指令或指定人
相关短句/例句
instruction cache指令Cache
1.To improve the operating efficiency of general micro processors,the architecture and design method ofinstruction cache are investigated.为提高通用微处理器的执行效率,研究了高性能指令Cache的体系结构和设计方法。
2.Most modern microprocessors employ on-chip caches to bridge the enormous speed disparities between the main memory and central processing unit (CPU), but these caches consume a significant fraction of total energy dissipation, especially the power dissipated byinstruction cache itself is often a significant part of the power dissipated by the entire on-chip caches.现代微处理器大多采用片上Cache来缓解主存储器与中央处理器(CPU)之间速度的巨大差异,但Cache也成为处理器功耗的主要来源,尤其是其中大部分功耗来自于指令Cache。
3.Instruction prefetching is an effective mechanism to reduce theinstruction cache miss rate.指令预取技术能够有效地降低指令Cache的访问失效率,提高微处理器的取指令能力,进而提高微处理器的性能。
3)instruction cache design指令Cache设计
1.This paper analyzes the traditional instruction prefetch technologies,studies a new instruction prefetch technology based on the communications between compilers and processors with the Explicitly Parallel Instruction Computing architecture, and gives a L1instruction cache design scheme supporting several technologies.本文分析了传统的指令预取技术,并结合显性指令并行计算(EPIC)体系结构,研究了基于编译器与处理器通信的新的指令预取技术,提出了一种支持多种预取技术的L1指令Cache设计方案。
4)command analyse指令分析
5)Cache Analysiscache分析
6)Cache behavior analysisCache行为分析
延伸阅读
指令指定计算机的操作和操作数或操作数地址的一组字符代码。由操作码和地址码组成。可被中央处理机理解和执行。操作码规定计算机操作的性质，地址码指出操作数所在地址和操作结果要送往的地址。参见“指令系统”。
